This application claims benefit of priority under 35 USC 119 to Japanese Patent Application No. 2001-5346, filed on Jan. 12, 2001, the entire contents of which are incorporated by reference herein.
The present invention relates to a differential amplifier circuit.
A differential amplifier circuit is used to amplify a voltage difference between two signals. The average of the voltages of two signals is called an in-phase input voltage, and the range of in-phase input voltages within which the differential amplifier circuit can normally operate is called an in-phase input voltage range. The differential amplifier circuit is more convenient with higher performance in a wider in-phase input voltage range.
FIG. 4 shows an example of a differential amplifier circuit concerning the present invention. The source and back gate of a P-channel MOS transistor MP3 are connected as a current source to a first power supply terminal VDD, and its gate receives a reference voltage Vref1.
The drain of the transistor MP3 is connected to the sources of P-channel MOS transistors MP1 and MP2; and its back gate, to the first power supply terminal VDD. The gate of the transistor MP1 is connected to an input terminal IN(xe2x88x92); and that of the transistor MP2, to an input terminal IN(+).
The drain and gate of an N-channel MOS transistor MN1 are connected to the drain of the transistor MP1; and its source and back gate, to a second power supply terminal VSS. The drain of an N-channel MOS transistor MN2 is connected to that of the transistor MP2; its gate, to the gate and drain of the transistor MN1; and its source and back gate, to the second power supply terminal VSS.
Voltages, currents, and the like when the transistors MP1 to MP3, MN1, and MN2 are generically called a transistor MXK will be called as follows:
VGSXK: gate-source voltage of MXK
VDSXK: drain-source voltage of MXK
IDXK: drain current of MXK
xcexcSXK: mobility of MXK
WXK: gate width of MXK
LXK: gate length of MXK
VthXK: threshold voltage of MXK
An in-phase input voltage CMVIN in this differential amplifier circuit is calculated from a xe2x80x9csecond power supply terminal VSSxe2x86x92transistor MN1xe2x86x92transistor MP1xe2x86x92input terminal IN(xe2x88x92)xe2x80x9d path:
CMVIN=VSS+VGSN1+|VDSP1|xe2x88x92VGSP1|xe2x80x83xe2x80x83(1)
As the input voltage is decreased, |VDSP1| decreases. The case wherein the operating point of the transistor MP1 coincides with the boundary between a saturation range and a non-saturation range can be regarded as a lower limit value CMVIN(L)1 of the in-phase input voltage range.
Assuming that the drain-source voltage VDS of the transistor MP1 at this time be an ON voltage VDS(ON)P1, we have
|VDS(ON)P1|=|VGS|xe2x88x92|Vth|xe2x80x83xe2x80x83(2)
as shown in FIG. 5.
Substituting equation (2) into equation (1) yields
CMVIN(L)1=VSS+VGSN1+|VDS(ON)P1|xe2x88x92|VGSP1|xe2x80x83xe2x80x83(3)
CMVIN(L)1=VSS+VGSN1xe2x88x92|VthP1|xe2x80x83xe2x80x83(4)
On the other hand, a MOS transistor which operates in the saturation range satisfies
VGS=(2ID/xcexcS*C0X*(W/L))1/2+Vthxe2x80x83xe2x80x83(5)
where ID: drain current, xcexcS: mobility, C0X: gate capacitance, W: gate width, and L: gate length.
The transistor MN1 always operates in the saturation range because the gate and drain voltages are the same. Substituting equation (5) into equation (4) yields the lower limit value CMVIN(L)1 of the final in-phase input voltage range:
xe2x80x83CMVIN(L)1=VSS+(2IDN1/xcexcSN1*C0X*(WN1/LN1))1/2+VthN1xe2x88x92|VthP1|xe2x80x83xe2x80x83(6)
The lower limit value CMVIN is calculated from a xe2x80x9cfirst power supply terminal VDDxe2x86x92transistor MP3xe2x86x92transistor MP1xe2x86x92input terminal IN(xe2x88x92)xe2x80x9d path:
CMVIN=VDDxe2x88x92|VDSP3|xe2x88x92|VGSP1|xe2x80x83xe2x80x83(7)
As the input voltage is raised, the voltage |VDSP3| decreases. The case wherein the operating point of the transistor MP3 coincides with the boundary between the saturation range and the non-saturation range can be regarded as an upper limit value CMVIN(H)1 of the in-phase input voltage range. This value is given by
CMVIN(H)1=VDDxe2x88x92|VDS(ON)P3|xe2x88x92|VGSP1|xe2x80x83xe2x80x83(8)
From equations (2) and (8), the upper limit value CMVIN(H)1 is
CMVIN(H)1=VDDxe2x88x92|VGSP3|+|VthP3|xe2x88x92|VGSP1|xe2x80x83xe2x80x83(9)
The operating point of the transistor MP1 is in the saturation range. Equation (5) for the saturation range also holds for MP3 whose operating point is at the boundary. Thus, from equations (5) and (9), the upper limit value CMVIN(H)1 is:
CMVIN(H)1=VDD+(2|IDP3|/(xcexcSP3*C0X*WP3)/LP3))1/2xe2x88x92(2|IDP1|/(xcexcSP1*C0X*WP1)/LP1)1/2xe2x88x92|VthP1|xe2x80x83xe2x80x83(10)
The in-phase input voltage range CMVIN1 is given by
CMVIN1=CMVIN(H)1xe2x88x92CMVIN(L)1xe2x80x83xe2x80x83(11)
Assuming that the threshold voltages of the P- and N-channel MOS transistors are equal and VthN1=VthP1, the in-phase input voltage range is from CMVIN(H)1 to CMVIN(L)1, as shown in FIG. 6. Near the second power supply voltage VSS or the first power supply voltage VDD out of this range, some transistor operates in the non-saturation range and does not normally operate as a differential amplifier circuit.
The differential amplifier circuit suffers a problem that it cannot normally operate upon reception of a voltage exceeding the in-phase input voltage range given by equation (11).
A differential amplifier circuit according to an aspect of the present invention comprises a differential amplifier unit which has first and second input terminals and differentially amplifies first and second input signals respectively input to the first and second input terminals, a first voltage shift unit which is connected to a first external input terminal and the first input terminal, decreases the first external input signal by a first voltage when a first external input signal input from the first external input terminal is at high level or decreases the first external input signal by a second voltage smaller than the first voltage when the first external input signal is at low level, and supplies the resultant first external input signal as the first input signal to the first input terminal, and a second voltage shift unit which is connected to a second external input terminal and the second input terminal, decreases the second external input signal by the first voltage when a second external input signal input from the second external input terminal is at high level or decreases the second external input signal by the second voltage when the second external input signal is at low level, and supplies the resultant second external input signal as the second input signal to the second input terminal.
A differential amplifier circuit according to another aspect of the present invention comprises a differential amplifier unit which has first and second input terminals and differentially amplifies first and second input signals respectively input to the first and second input terminals, a first voltage shift unit which is connected to a first external input terminal and the first input terminal, reduces a range of high to low levels of a first external input signal input from the first external input terminal, and supplies the resultant first external input signal as the first input signal to the first input terminal, and a second voltage shift unit which is connected to a second external input terminal and the second input terminal, reduces a range of high to low levels of a second external input signal input from the second external input terminal, and supplies the resultant second external input signal as the second input signal to the second input terminal.